The Dual Digital Shift Register is an Aleatoric sequence generator based around shift registers. It offers a unique take on sequence generation, using gate signals to create pseudo-random chance operations. It creates patterns based on the relationship between the clock and data inputs.
It has 2 channels, each with 2 inputs and 5 outputs. The inputs are both gate inputs and are labeled clock and data. The outputs are 4 gate outputs, labeled QØ, Q1, Q2, & Q3 and a cv output.
If the data input is high (above .5v) when the clock is triggered, a bit is added to the shift register and the QØ will output high gate - When the unit is clocked, the bit value will cascade from QØ to Q1 to Q2 and onwards. Gate output Q3 is internally combined with the data jack in an XOR configuration (so if either is high, it is considered gate high at the data input or if both are high or low it is considered gate low at the data input.
The real fun is the CV output - the CV output will output a value equal to the binary value of the four bits (1 of 16 states), with CV output 1 producing 16 values in the range of 0-3.1v and CV output 2 producing 16 values in the range of 0-4.3v.
Feed clocks and gates and CV into the DDSR to produce 2 different psudo-random cv sequences!
It can be predictable if given closely related signals, which can repeat or subtlely morph between different rhythmic expressions. The DDSR settles into patterns and then moves away from them, there are periods when it will grab sequences and loop them. The sequences it creates are based around loops instead of random uncorrelated voltages and because of that the results are musical and familiar.
80 mA +12V
31 mA -12V
0 mA 5V
DDSR Manual
It has 2 channels, each with 2 inputs and 5 outputs. The inputs are both gate inputs and are labeled clock and data. The outputs are 4 gate outputs, labeled QØ, Q1, Q2, & Q3 and a cv output.
If the data input is high (above .5v) when the clock is triggered, a bit is added to the shift register and the QØ will output high gate - When the unit is clocked, the bit value will cascade from QØ to Q1 to Q2 and onwards. Gate output Q3 is internally combined with the data jack in an XOR configuration (so if either is high, it is considered gate high at the data input or if both are high or low it is considered gate low at the data input.
The real fun is the CV output - the CV output will output a value equal to the binary value of the four bits (1 of 16 states), with CV output 1 producing 16 values in the range of 0-3.1v and CV output 2 producing 16 values in the range of 0-4.3v.
Feed clocks and gates and CV into the DDSR to produce 2 different psudo-random cv sequences!
It can be predictable if given closely related signals, which can repeat or subtlely morph between different rhythmic expressions. The DDSR settles into patterns and then moves away from them, there are periods when it will grab sequences and loop them. The sequences it creates are based around loops instead of random uncorrelated voltages and because of that the results are musical and familiar.
Specifications:
8 HP80 mA +12V
31 mA -12V
0 mA 5V
DDSR Manual
